This invention generally relates to device and device fabrication and, more particularly, to transistor-trench capacitor memory cells.
Integrated circuits (ICs) employ capacitors for the storage of charge. The presence or absence of stored charge, its charge storage state, defines information contained within capacitors in ICs. For example, memory devices, including random access memories (RAMs), such as dynamic RAMs (DRAMs), store charge in capacitors; the relative quantity of charge in the capacitor is commonly used to represent a bit of data (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d).
A DRAM IC includes an array of memory cells interconnected by rows and columns of conductive lines. The rows and columns of conductive lines are typically referred to as wordlines and bitlines, respectively. Cells in the memory array may be randomly accessed, for reading or writing bits of data, by activating appropriate wordlines and bitlines.
A DRAM memory cell typically includes an access transistor that is connected serially with a storage capacitor. Typically, the access transistor of a DRAM memory cell consists of a metal-oxide-semiconductor field effect transistor (MOSFET). The MOSFET includes a semiconductor body (substrate) of a first conductivity type and first and second regions of the opposite conductivity type which are separated by a portion of the substrate which is covered by a gate conductor that is separated from the surface of the substrate by a dielectric layer. The first and second regions are referred to as bitline and storage node diffusion (also commonly referred to as the buried-strap outdiffusion) regions or first and second input/output region, and comprise the drain and source regions of the MOSFET. The diffusion region which serves as the drain or source depends upon the operation of the transistor within the memory cell (i.e., write xe2x80x9c1xe2x80x9d, write xe2x80x9c0xe2x80x9d, read xe2x80x9c1xe2x80x9d, read xe2x80x9c0xe2x80x9d, data refresh). For each memory cell, the gate of the MOSFET is connected to a wordline conductor, the bitline diffusion is connected to the bitline conductor, and the storage node diffusion is connected to the storage capacitor. Application of a voltage to the wordline (active state) switches MOSFETs connected to that wordline to the on-state (conductive), allowing the exchange of charge between the bitline and the storage capacitor. When the MOSFET is in the on-state memory cell operations such as write xe2x80x9c1xe2x80x9d, write xe2x80x9c0xe2x80x9d, read xe2x80x9c1xe2x80x9d, read xe2x80x9c0xe2x80x9d, and data refresh may be performed. MOSFETs connected to wordlines which are inactive are in the off-state (non-conductive). In the off-state the MOSFET isolates the storage capacitor from the bitline. This allows charge stored in the capacitor, which represents a stored logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, to be retained for a useful period of time.
Trench capacitors are commonly used as storage elements in DRAMs. A trench capacitor is a three-dimensional structure formed into a semiconductor substrate. A conventional trench capacitor comprises a trench etched into a silicon substrate. The trench is typically lined with an insulating material that serves as the dielectric of the storage capacitor. A first electrode of the storage capacitor consists of a conductive material, typically n+ type doped polysilicon, which fills a portion of the trench. The first electrode is typically referred to as the capacitor node. A second electrode of the storage capacitor, the capacitor plate (or counter-electrode), is formed by a diffused region adjacent a lower portion of the trench sidewall. The diffused plate electrode (also commonly referred to as the buried-plate diffusion) is typically formed by outdiffusing n+ type dopant, from a dopant source within the trench, into the p-type doped substrate surrounding a lower portion of the trench, and is commonly referred to as the buried-plate electrode. To assure an adequate time of retention of data (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) stored in the capacitor when the MOSFET of the memory cell is in the off-state, leakage current to and from the capacitor node must typically be less than 1fA/cell.
FIG. 1 shows a prior art vertical MOSFET-trench capacitor DRAM cell including a vertical access MOSFET having a gate conductor 32, a bitline diffusion (a first input/output region) 25, and a storage node diffusion (a second input/output region) 22 formed in a semiconductor body (substrate) 20 having a top surface 13. The vertical MOSFET overlies a storage capacitor within the trench. Storage node diffusion 22 is electrically connected to a storage capacitor consisting of a storage capacitor node electrode 17 (typically of n+ type doped polysilicon), a capacitor dielectric 15 layer (typically a silicon nitride/silicon oxide sandwich), and a buried-plate diffusion electrode 12 (typically an n+ type doped pocket in a p-type doped region of a monocrystalline silicon substrate). A junction between the p-type doped substrate region (also referred to as the array p-well) 20 and a band of n-type dopant 14 is denoted by 28. The band of n-type dopant 14 serves to isolate the p-type doped substrate region of the cell from other circuit elements on the chip. Leakage of charge to and from storage capacitor node electrode 17 may result from a variety of mechanisms. Sub-threshold conduction between bitline diffusion 25 and storage node diffusion 22 of the MOSFET, storage node diffusion 22 leakage to substrate 20, and parasitic MOSFET action between storage node diffusion 22 and buried-plate diffusion electrode 12 are mechanisms that typically contribute to leakage resulting in loss of stored data. Sub-threshold leakage may be limited by appropriate choice of threshold voltage of the MOSFET. Storage node diffusion 22 to substrate 20 leakage may be controlled by methods such as limiting the maximum substrate doping concentration adjacent to storage node diffusion 22 and appropriate anneal conditions during fabrication. However, as the dimensions of the DRAM cell are scaled down, control of the parasitic MOSFET action between storage node diffusion 22 and buried-plate diffusion electrode 12 becomes increasingly problematic.
To limit parasitic MOSFET leakage between storage node diffusion 22 and buried-plate diffusion electrode 12 to an acceptable level, an isolation collar 16, typically of silicon oxide, is provided therein on a sidewall of the trench between storage node diffusion 22 and buried-plate diffusion electrode 12. The parasitic MOSFET comprises source/drain diffusions consisting of storage node diffusion 22 and buried-plate diffusion 12, with the gate conductor of the parasitic MOSFET being storage capacitor node electrode 17. Isolation collar 16 is the equivalent gate dielectric of the parasitic MOSFET. By increasing the thickness of the isolation collar 16, the threshold voltage of the parasitic MOSFET may be increased, reducing its off-state leakage current. Typically, an isolation collar thickness of between approximately 25-70 nm is required to reduce the parasitic leakage current to 1fA/cell or less.
Continued demand for DRAM with ever increasing density of bits/chip requires that the design groundrules be aggressively reduced. For example, design rules have been scaled from 0.25 microns (xcexcm) down to below 0.12 xcexcm. The shortest dimension for the opening of the storage trench is typically approximately equal to the design rule. At a design rule of 0.25 xcexcm there is ample room within the trench to form an isolation collar 16 as thick as 70 nm and still fill the trench with storage node capacitor electrode material 17. However, as design rules are reduced below 0.12 xcexcm, processing of a trench capacitor having an isolation collar sufficiently thick to reduce the parasitic MOSFET leakage current to 1A/cell or less becomes increasingly difficult. Smaller trench openings necessitate a corresponding reduction in isolation collar thickness to facilitate filling of the trench with storage node capacitor electrode material 17. However, to reduce the parasitic leakage to an acceptable level, the thickness of the isolation collar 16 needs to be about 25-70 nm, depending on operating voltage conditions. Such a thick isolation collar hinders the filling of the smaller trench and also increases the series resistance of the storage capacitor within the trench, due to the smaller cross-sectional area of the conductive material 17 confined by isolation collar 16.
Another technique of raising the threshold voltage of the parasitic MOSFET and reducing its off-state leakage is to increase the dopant concentration in the substrate between storage node diffusion 22 and buried-plate diffusion electrode 12. However, raising this dopant concentration increases the electric fields in the depletion regions. This results in a sharp increase in storage node diffusion 22 to substrate 20 leakage current which causes a corresponding decrease in the data retention time. This is especially true when silicon crystallographic defects are present and when the p-well doping concentration adjacent storage node diffusion 22 exceeds approximately 6xc3x971017 atoms/cm3.
One prior art structure uses a structure and method of forming an annular region of higher dopant concentration localized between the storage node diffusion and the buried-plate diffusion of a trench capacitor DRAM cell. This technique limits the vertical extent of the region of higher dopant concentration such that the substrate doping adjacent the storage node diffusion and, hence, the junction leakage are not significantly increased. However, for the technique to be effective in reducing parasitic MOSFET leakage while avoiding high substrate doping adjacent the storage node diffusion, a minimum separation of approximately 0.8 xcexcm between storage node diffusion and buried-plate diffusion is required. Accordingly, for a given trench depth, the portion of trench sidewall area containing the capacitor dielectric 15 is reduced. This results in the capacitance of storage capacitor being reduced.
It is desirable to provide a structure and method for a fabricating a trench capacitor with enhanced time of charge retention and an isolation collar which is thinner than other prior art trench capacitor structures.
From a first apparatus aspect the present invention is a semiconductor apparatus comprising a semiconductor body defining a trench therein and being of a first conductivity type, first and second semiconductor regions, and a trench. The first and second semiconductor regions are of a second conductivity type that is opposite the first conductivity type. The regions are located within the semiconductor body and are separated by a portion of the semiconductor body. Each of the first and second semiconductor regions shares a section thereof which defines portions of a wall of the trench. A part of the portion of the semiconductor body between the first and second semiconductor regions defines a void which extends around the perimeter of the trench. The wall of the trench is lined with an insulating layer that separates the void from the trench and separates the second semiconductor region from the trench. The trench is filled with a conductive material that contacts the section of the first semiconductor region that defines a portion of the wall of the trench.
From a second apparatus aspect the present invention is a transistor-capacitor memory cell comprising a semiconductor body defining a trench therein and being of a first conductivity type, first, second and third regions, and a conductive material. The first, second, and third semiconductor regions are of a second conductivity type that is opposite the first conductivity type. The regions are located within the semiconductor body and are separated by portions of the semiconductor body. The first and second semiconductor regions are first and second input/output regions of the transistor of the memory cell. A gate of the transistor is located between a portion of the semiconductor body between the first and second input/output regions and is separated therefrom by a gate dielectric layer. Each of the second and third semiconductor regions has a section thereof which defines portions of a wall of the trench. A part of the portion of the semiconductor body between the second and third semiconductor regions defines a void which extends around the perimeter of the trench. Portions of the wall of the trench are lined with a first insulating layer that separates the void from the trench and separates the third semiconductor region from the trench. The insulation lined trench is filled with a conductive material that contacts the portion of the second semiconductor region that defines a portion of the wall of the trench. The conducive material, insulating layer, and third semiconductor region serving as the capacitor of the memory cell.
From a third apparatus aspect the present invention is a semiconductor apparatus comprising a semiconductor substrate, a first n+ type conductivity region, a first dielectric layer, a second n+ type conductivity region, a p-type conductivity region, a second dielectric layer, and conductive material. The semiconductor substrate defines a trench therein which has at least one wall. The first n+ type conductivity region abuts the wall of the trench at a lower portion of the trench. The first dielectric layer covers the part of the wall of the trench and is located over the portion of the first n+ type conductivity region. The second n+ type conductivity region abuts at least one of the wall in an upper portion of said trench. The p-type conductivity region is within the semiconductor substrate and is positioned between the first and second n+ type conductivity diffusion regions. The second dielectric layer covers portions of the wall of the trench positioned between the first and second n+ type conductivity diffusion regions. A portion of the p-type conductivity region defines a continuous void therein which intersects the wall of the trench and encircles the perimeter of said trench and is positioned between said first and second n+ type conductivity diffusion regions. A conductive material is disposed within the dielectrically lined trench.
In a first method aspect the present invention is a method, starting with a semiconductor body of a first conductivity type in which there has been formed a trench with a first region of a second conductivity type in contact with a lower portion of a wall of the trench and a first insulating layer covers the wall of the trench. The method comprises the steps of: filling a lower portion of the trench with conductive material; forming an opening in the first insulating layer above the first region and the conductive material such that a portion of the semiconductor body is exposed with said exposed portion being separated from the first region by other portions of the semiconductor body; forming through the opening a void in the semiconductor body, said void encircling the trench; forming a second insulating layer so as to close the opening in the first insulating layer; filling a portion of the trench above the first conductive material with a second conductive material; and forming a second region of a second conductivity type in a portion of the semiconductor body displaced from the.void by portions of the semiconductor body, said second region being in contact with the second conductive material.
From a second method aspect the present invention is a method of making a semiconductor structure. The method comprises the steps of: forming in a semiconductor substrate a trench which has a wall defined by a portion of the semiconductor substrate; forming a capacitor in a lower portion of said trench, said capacitor having a first n+ type conductivity diffusion region abutting the wall in a lower portion of said trench, said first n+ type conductivity diffusion region defining a first electrode of said capacitor; forming a node dielectric within said lower portion of said trench, said node dielectric overlying said first n+ type conductivity diffusion region; filling lower portion of said trench with a first conductive material, said first conductive material defining a second electrode of said capacitor; forming an insulating layer over top surface of said first conductive material; forming an etch barrier material on the wall of an upper portion of said trench; removing said insulating layer over the top surface of said first conductive material so as to provide an exposed semiconductor portion of the wall not covered by said etch barrier material, said exposed portion of the wall encircling said trench; etching a void into said exposed semiconductor substrate portion of the wall not covered by said etch barrier material, said void being continuous about the perimeter of said trench; depositing a conformal insulating material on exposed surfaces, said conformal insulating material lining the interior region of said void, wherein said conformal insulating material pinches off the opening to said void; filling upper portion of said trench with a second conductive material, said second conductive material contacting said first conductive material; forming a second n+ type conductivity region abutting the wall in an upper portion of said trench, said second n+ type conductivity region defining one of input/output regions of a field effect transistor; and forming a p-well region in said semiconductor substrate positioned between said first n+ type conductivity region and said second n+ type conductivity region.
The present invention will be better understood from the following more detailed description taken in conjunction with the drawings and claims.